delay envelope follower

Haible_Juergen#Tel2743 HJ2743 at denbgm3xm.scnn1.msmgate.m30x.nbg.scn.de
Wed Feb 28 21:20:00 CET 1996


>     An idea for an ideal solution I've seen proposed is to use a tapped
>     analog delay line, with a delay time equal to slightly more than the
>     period of the lowest input frequency of interest, with all taps summed 

>     together with diodes. With this design, the highest voltage on any of
>     the taps will be the output of the device, and no ripple filter is
>     required. On paper this looks like the perfect envelope follower, with 

>     the fastest possible response time. Anybody out there ever done this?

Not done. But it sounds good, because we'd have all degrees of freedom:
Clock rate -> highest frequency detected
Length -> lowest frequency detected
Number of tabs -> ripple of VC

(just from first glance; so please correct me)

For a low ripple, we'd have to use a lot of (pecicion) rectifiers, so
somewhere there must be a break even between a number of
cascaded rectifiers and the delay line.

JH.



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