gate voltage and logic stds

gstopp at fibermux.com gstopp at fibermux.com
Fri Feb 2 23:16:09 CET 1996


     'Ere's my take on this subject:
     
     First off I should say that I'd need to see the circuit in Barry's 
     book to give any ideers about it, and I haven't seen any EG designs 
     that use V- on the 4016. But that doesn't mean that they aren't 
     around, that just means that I haven't seen them.
     
     Generally for TTL and CMOS, V+ = logic "1" and ground = logic "0", 
     regardless of where it comes from. As far as flip-flops go, the logic 
     level required to set or reset is arbitrary - for example, a 
     cross-coupled NAND gate RS flip-flop needs both set and reset high in 
     the quiescent state, and a logic "0" on the Q-side gate to set it and 
     a logic "0" on the Q-NOT-side gate to reset it. The same flip-flop 
     made out of NOR gates has set and reset in a logic "0" state normally, 
     and a logic "1" on the Q-NOT-side gate will set the Q output to a 
     logic "1". So you see "1" and "0" are always high vs. low in voltage 
     (except in async communications, there's always gotta be an exception 
     right?), but "set" and "reset" are not necessarily related to any 
     specific levels.
     
     Hope that helps.
     
     - Gene
     gstopp at fibermux.com


______________________________ Reply Separator _________________________________
Subject: gate voltage and logic stds
Author:  ldavid at lae.lad.gmeds.com at ccrelayout
Date:    2/2/96 2:46 PM


Greetings Knowers,
     
I'm reading through Barry Klein's book (finally!) and while I'm finding 
it generally excellent, I am a little confused.  Right now I'm looking 
at the ADSR ckt on pg. 56 (based on an RS flip-flop, a 4016 switch, 
comparators at trig and gate in, buffered output etc.).  From the 
description, it appears that:
     
For logic gates and switches
     
  logic 0 = V+ or gnd
  logic 1 = V-
     
For gate CV signals
     
  logic 0 = 0V
  logic 1 = 10V
     
Is this right?  So e.g., a V- voltage at a NOR gate or a CMOS switch 
will act as a logic 1; and any voltage between 0 and V+ will act as a 
logic 0.  
     
What's confusing is that he says that when the output of the 
gate CV comparator is high, it is a logic 0.  Later he says that a high 
output from another comparator sets the flip-flop, implying that it is a 
logic 1.  I must be missing something.  Help?
     




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