Idea for a CV quantizer

[Christopher List]

Hi!

Some time ago there was a question about a simple CV quantizer.
My answer back then was using an ADC abd a DAC, the DAC having
much more bits than the 6 or 7 that give you the desired resolution,
but with only these 6 or 7 bits *connected* to the ADC. This was to
achieve the desired accuracy which has to be far better than the
resolution.

Meanwhile I have found a better technique, both in an old Electronotes
issue and in the ARP Sequencer circuits. Here there is only a DAC
required. A counter cycles thru all possible values of the DAC
permanently, producing a staircase voltage.
A comparator compares the input CV with the staircase voltage and
fires a S&H as soon as the staircase approaches the CV. This
quantized CV is then held until the next cycle.
This design has two great advantages:
(1) You don't need an ADC,  and
(2) you only need one DAC for as many quantizer channels you want:
      just give each channel its own Comparator and S&H.
You still need a good DAC for this, however. So either you have to buy
a 12 or better 14-bit DAC (not easy to come by if you don't want a serial
input, nowadays!), or you have to build your own discrete DAC (low
resolution, but high accuracy).

Now here is the idea (don't really think that it is new; but I haven't seen
it anywhere, so far):
All you need is a precise staircase; no need to implement it with a
DAC and counter!
I was thinking about this old Integrator + Charge pump approach.
Build an integrator with an opamp, add a thyristor or some other
reset-device that discharges the cap way above the desired CV
range. Then take a pulse oscillator, clip the amplitude with some
precise voltage reference (adjustable, for exact 1/12 V steps),
and feed this into the integrator.

I am not sure how good this would work. Would I get the desired accuracy
of +/- 1 cent with standard components?
I would aim for a conversion rate of 1ms. So with a clock rate of 100kHz
I should be able to cover 88 notes.

What do you think ??
(I *feel* that there must be some week spot in this idea, but I just
can't see it at the moment!)
How precicely can a charge pump/integrator system work?
What would I have to consider?

Any comments welcome,

JH.

To: HJ2743 @ denbgm3xm.scnn1.msmgate.m30x.nbg.scn.de @ Internet, gstopp @ 
fibermux.com @ Internet, jocke @ netcontrol.fi @ Internet, synth-diy @ 
horus.sara.nl @ Internet
cc:  (bcc: Christopher List)
From: don @ till.com (Don Tillman) @ Internet @ WORLDCOM
Date: 02/28/96 11:53:01 AM CST
Subject: Re: Idea for a CV quantizer

   From: Haible_Juergen
   Date: Wed, 28 Feb 96 18:45:00 PST

   >One word: drift.

   the integrator would be reset to zero every millisecond,
   so this one shouldn't drift away.

Oh okay, I misunderstood your idea. Yeah, it should be fine.

But you can simplifiy it a lot; since you'll be S/H-ing anyway you
don't really need a stepping integrator.  Use a regular sawtooth
integrator, a counter, a comparator, a S/H, and only allow the S/H to
be triggered on the counter clock pulse.  Easy.


The reason I misunderstood it was because I had a preconceived idea in
my mind of a closed loop system, where the DAC (or your pulse
integrator) output gets compared to the input voltage and you goose
the counter (or integrator) when the difference between the input
signal and the DAC/integrator output is beyond one quantum, high or
low.

I think this approach simplifies things, but the drift wouldn't allow
the pulse integrator approach to work, it would have to be a DAC.  It
can also have variable hysteresis, if that might be considered a
feature.

I'm also thinking there must be a way to use a standard successive-
aproximation DAC chip with no extra hardware.

  -- Don

To: synth-diy @ horus.sara.nl (DIY) @ Internet, till @ netcom.com @ Internet
cc:  (bcc: Christopher List)
From: HJ2743 @ denbgm3xm.scnn1.msmgate.m30x.nbg.scn.de (Haible_Juergen#Tel2743) 
@ Internet @ WORLDCOM
Date: 02/29/96 10:55:00 AM CST
Subject: AW: Re: Idea for a CV quantizer


> But you can simplifiy it a lot; since you'll be S/H-ing anyway you
> don't really need a stepping integrator.  Use a regular sawtooth
> integrator, a counter, a comparator, a S/H, and only allow the S/H to
> be triggered on the counter clock pulse.  Easy.

Yes, I came to something similar last night! Just two sawtooth generators,
one with approx. 100 times the frequency of the other. It is important
that the fast one is hard-synced to the slow one to eliminate a
random offset. The two generators would be identical and connected
to the same voltage reference, only one cap would be 100 times
larger than the other. So a lot of the possible drift effects should
cancel out ...
Every time when the slow sawtooth crosses the input CV, the next
reset pulse of the fast sawtooth is used to sample the CV.
Every time the slow sawtooth reaches its upper limit (beyond the
input CV range), both generators are reset by discharching the caps.

I *hope* this should be accurate enough. If we even can build VCO's that
track to each othe rover decades, it should be simple to build
fixed frequency oscillators that keep their frequency relative to each
other!
The main problem which I still see, is that any jitter of the sample pulses
would cause some voltage error, and I'm not sure if I can keep all
the propagation delays constant enough!
100kHz means 100us for a semitone, this means 100ns for one Cent.
Do you think it is achievable to keep the long-time ( 1 day) drift below
these 100ns? The staircase approach would have the advantage
of being less sensitive to this ... I'm really not sure yet what would be 
better.


JH.


To: synth-diy @ horus.sara.nl @ Internet
cc:  (bcc: Christopher List)
From: gstopp @ fibermux.com @ Internet @ WORLDCOM
Date: 02/29/96 01:52:06 PM CST
Subject: Re[2]: Idea for a CV quantizer

     Juergen,
     
     I've had very good results from 6-bit R-2R ladders for semitone 
     intervals at 1v/octave. I match 1% resistors with a DVM first just to 
     be safe.
     
     Summing resistors I've never tried, and it seems to me that you would 
     need a trimpot for every bit.
     
     I know that Joachim likes the chip DAC idea, but I once had back luck 
     with a 1408 and have not tried any chip since (maybe it's a good 
     approach and I just don't know it).
     
     Guidelines - make sure your bits go between exactly between zero volts 
     and VCC, and use resistors in the 1K-50K range, and all will be 
     stable.
     
     - Gene


To: gstopp @ fibermux.com ("'GStopp'") @ Internet, synth-diy @ horus.sara.nl 
(DIY) @ Internet
cc:  (bcc: Christopher List)
From: HJ2743 @ denbgm3xm.scnn1.msmgate.m30x.nbg.scn.de (Haible_Juergen#Tel2743) 
@ Internet @ WORLDCOM
Date: 02/29/96 11:00:00 AM CST
Subject: Re: Idea for a CV quantizer


>     My impression is that this would not be any easier than a DAC, and
>     probably less accurate. For the DAC approach all you would need is a
>     clock, a counter (4040?), an bunch of resistors, and a buffer (maybe). 

>     However the DAC will be very clean and sterile, so perhaps the charge
>     pump can offer some interesting analog-ish deviations.
>
>     -Gene

Gene, I am not very experienced in discrete DACs. I know that you
have made some already. What I need is a precise 7-bit DAC,
because I have to cover at least -1V to +5V (so a 6-bit isn't enough).
What I fear is the temperature drift of the buffers impedance that
might be different from the external resistors' drift.
Would You suggest a discret R/2R ladder or just 7 different summing
resistors?

JH.

To: synth-diy @ horus.sara.nl (DIY) @ Internet, till @ netcom.com @ Internet
cc:  (bcc: Christopher List)
From: HJ2743 @ denbgm3xm.scnn1.msmgate.m30x.nbg.scn.de (Haible_Juergen#Tel2743) 
@ Internet @ WORLDCOM
Date: 03/07/96 04:53:00 PM CST
Subject: AW: Re: AW: Re: Idea for a CV quantizer


> Oscillator running at roughly 100 KHz drives a divide-by-100 counter

Also a good idea! So the fast oscillator would reset the slow one.
But what exactly would be the advantage?

Anyway, I have decided to use a DAC now. Thanks to Joachim who
trades me a 12 bit DAC, it is the easiest way to go now. (Though I
would really have liked to try the other approach!)
I will make a slight change to the usual design, however:
Now what I want is a counter that cycles fast until the comparator
fires, and then rests on this number for some time. This could
be achieved with an Inhibit input at the counter. The comarator
triggers a monoflop. The monoflop controls both, the S&H stage
and the counter Inhibit. When the monflop falls back, the counter
goes on, until another input channel's comparator fires. This way
the sampling time / counting time ratio would be greatly enhanced!

I have made the schematics for this last night. I will build a dual
quantizer, i.e. 2 independent channels that share one counter and dac.

I use one LM339 quad comparator for the CV/staircase comparison
and the monoflops.
The DAC is an AM6012. The counter is a CD 4060, which has an internal
clock oscillator. The clock enable is made by simply forcing one pin
of the oscillator gates to High as long as either of the monoflops are
on.  As the monoflops are made of comparators, they have a +/-15V
swing and can control the S&H FETs (BF245) directly, without level shift.
5 opamps are required. Two serve as S&H buffers (either two LF356's or
a LF353 plus network for driving capacitice cables), one as a I/V converter
for the DAC, and the remaining two are needed for a level shift between
the comparator and the DAC. Why a level shift?
For quantizing continuous signals (sequencer potentiometers ...) I
wouldn't need it, but if I drive the quantizer with a standard keyboard
voltage (for example to enhance the accuracy of my Kenton Pro-2),
the input voltage would just always fall on the thresholds. So a shift of a
quatertone would be appropriate.

This project is on paper only so far - so any ideas are still welcome,
but layout / results isn't yet available.

JH.