gate voltage and logic stds

[ldavid at lae.lad.gmeds.com]

Greetings Knowers,

I'm reading through Barry Klein's book (finally!) and while I'm finding 
it generally excellent, I am a little confused.  Right now I'm looking 
at the ADSR ckt on pg. 56 (based on an RS flip-flop, a 4016 switch, 
comparators at trig and gate in, buffered output etc.).  From the 
description, it appears that:

For logic gates and switches

  logic 0 = V+ or gnd
  logic 1 = V-
  
For gate CV signals

  logic 0 = 0V
  logic 1 = 10V

Is this right?  So e.g., a V- voltage at a NOR gate or a CMOS switch 
will act as a logic 1; and any voltage between 0 and V+ will act as a 
logic 0.  

What's confusing is that he says that when the output of the 
gate CV comparator is high, it is a logic 0.  Later he says that a high 
output from another comparator sets the flip-flop, implying that it is a 
logic 1.  I must be missing something.  Help?

ld
--
----------------------------------~~~~~~~*--------------~~~~~~~*    
Larry David                    "I no longer live, 
ldavid at lae.lad.gmeds.com        but Christ lives in me."