Envelope Generators again

[gstopp at fibermux.com]

     Hi List,
     
     A few days ago I built an ADSR envelope generator out of some IC's and 
     a pair of DIP relays. The main reason for using relays in an ADSR 
     circuit was to eliminate (as best as possible) any errors resulting 
     from finite "on-resistance" of the integrating capacitor 
     charge-discharge elements. Since sluggish response is one of the main 
     complaints by users about the envelope generators found in some of the 
     various commercial synthesizers, I wanted to start from an idealized 
     case and work from there to come up with a design that looks as good 
     as possible on paper (or on a scope), with the fewest possible parts. 
     I want a bigger home-built system and I'm kinda lazy.
     
     Anyway it worked great. The minimum time constants for attack, decay, 
     and release were in the tens of microseconds, as opposed to the tens 
     of milliseconds minimum times advertised in commercial systems. After 
     messing with the timing logic and component values, I was able to 
     optimize the thing for modular system use. Then I turned back to the 
     idea of replacing the relays with solid-state components to see how 
     the parameters changed away from ideal.
     
     Since I based the charge/discharge logic on double-throw switches, the 
     first thing I tried was the 4053 triple 2-to-1 analog switch to 
     replace the relays. The timing performance did move away from the 
     ideal; however, the resulting numbers are actually better than most 
     spec-sheet numbers for commercial units, by a factor of 10 to 1 or 
     more.
     
     Here are the numbers for the ADSR using the 4053 analog switch, 1 Meg 
     pots, and a 4.7 microfarad integrating capacitor:
     
     Minimum Attack Time  = 50 microseconds
     Minimum Decay Time   = 1.5 milliseconds
     Minimum Release Time = 1 millisecond
     
     Maximum Attack Time  = 5 seconds
     Maximum Decay Time   = 6 seconds
     Maximum Release Time = 6 seconds
     
     Notice that the falling times are much longer than the rise time - 
     this is because the rise time is cut short when the attack peak level 
     is reached, rather than being allowed to charge up naturally, and the 
     falling times are natural (exponential) discharge curves. However -  
     most commercial synthesizers start at ten milliseconds and go up from 
     there. Changing the cap to 10uF doubles these numbers across the 
     board.
     
     The whole thing runs off of +5 volts and ground. The ADSR has a 
     maximum amplitude of about 4 volts. I intend to modify the whole thing 
     to run off of +15 volts since +5 isn't traditionally used in analog 
     systems.
     
     The timing logic consists of a pair of comparators whose inputs are 
     tied together but reversed, to provide a cleaned-up and buffered copy 
     of the input gate plus its inversion. These two signals then go to a 
     flip-flop made from a 4002 dual 4-input NOR gate. The gate is 
     differentiated by a cap to set the flip-flop, and the inverted gate 
     resets it. This provides the attack phase termination if the gate goes 
     away before the attack finishes.
     
     The output of the flip-flop controls the attack-decay analog switch. 
     The inverse of the gate controls the decay-release analog switch. The 
     integrating cap is buffered by an op-amp. which provides the ADSR 
     output. This output also goes through a "peak-trim" trimpot back into 
     the flip-flop to reset it to start the decay phase when the attack 
     finishes.
     
     Anyway I'll clean up the schematic and make it available by tomorrow 
     hopefully.
     
     - Gene
     gstopp at fibermux.com