[sdiy] Using dual BBD chips for higher clock frequency
didierleplae at yahoo.com
Fri Jun 17 05:20:50 CEST 2022
The datasheet for the MN3205 suggests a clock frequency from 10k to 100k. Giving a 204.8ms - 20.48ms delay time.
You could run at higher clock speeds, but you would just end up with shorter delay times.
The reason I came up with 18k filtering for 20k clock is because the Jan Hall electronotes circuit uses 9k filters for 10k clock.
At any rate, a higher frequency clock is just easier to filter out.
> On Jun 16, 2022, at 8:08 PM, Jay Schwichtenberg via Synth-diy <synth-diy at synth-diy.org> wrote:
> Isn't one of the advantages of using a BBD over a digital solution is the clocking can go to 500 KHz to 1MHz?
> So depending on the clock freq you can get the aliasing filters higher up and have better freq range.
> Jay S.
>> On 6/16/2022 4:38 PM, Tom Wiltshire wrote:
>>>> On 16 Jun 2022, at 23:11, Mike Bryant <mbryant at futurehorizons.com> wrote:
>>> You could add more BBDs in parallel and sum the outputs to reduce it again.
>> I think this is what's referred to in the SAD1024 datasheet. That chip was actually a dual 512-stage device, and one suggestion was to use the two delay lines in parallel for reduced noise. I don't remember the details. Could be that simply summing the signals gives you a +6dB boost in the signal, but not so much in the noise, or it could be that it recommended a differential signal. Can't remember, sorry. I found an "Archer"-branded version of the datasheet here which shows various possibilities:
>>> If lowest clock speed is 20k, you really need to be filtering out everything about 10k.
>> BBD datasheets generally recommend a conservative bandwidth of 1/3rd of the clock frequency, so 20K would be 6.67KHz. Poor, but much better than 3.3KHz!!
>> I totally agree that 18KHz filtering with 20KHz clock is not realistic. No practical filter is that sharp.
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