[sdiy] Using dual BBD chips for higher clock frequency
jschwich53 at comcast.net
Fri Jun 17 03:01:44 CEST 2022
Isn't one of the advantages of using a BBD over a digital solution is
the clocking can go to 500 KHz to 1MHz?
So depending on the clock freq you can get the aliasing filters higher
up and have better freq range.
On 6/16/2022 4:38 PM, Tom Wiltshire wrote:
>> On 16 Jun 2022, at 23:11, Mike Bryant <mbryant at futurehorizons.com> wrote:
>> You could add more BBDs in parallel and sum the outputs to reduce it again.
> I think this is what's referred to in the SAD1024 datasheet. That chip was actually a dual 512-stage device, and one suggestion was to use the two delay lines in parallel for reduced noise. I don't remember the details. Could be that simply summing the signals gives you a +6dB boost in the signal, but not so much in the noise, or it could be that it recommended a differential signal. Can't remember, sorry. I found an "Archer"-branded version of the datasheet here which shows various possibilities:
>> If lowest clock speed is 20k, you really need to be filtering out everything about 10k.
> BBD datasheets generally recommend a conservative bandwidth of 1/3rd of the clock frequency, so 20K would be 6.67KHz. Poor, but much better than 3.3KHz!!
> I totally agree that 18KHz filtering with 20KHz clock is not realistic. No practical filter is that sharp.
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