[sdiy] Using dual BBD chips for higher clock frequency
brianw at audiobanshee.com
Fri Jun 17 02:23:16 CEST 2022
I was going to suggest that differential would improve S/N by 3 dB, since the signal would get a 6 dB boost and the two chips' noise would sum to +3 dB because they should be uncorrelated.
Then I realized that differential (inverting one copy) wouldn't really be any better than maintaining the same polarity in both, since the noise is not going to cancel anyway. Note that balanced audio is differential because the noise is typically induced in the cable almost equally on both signal wires, so inverting the -signal will cancel most of the noise. Not the case with BBD noise because there would be no correlation between the noise in the two chips.
So, basically, you can still get that 3 dB improvement in S/N whether you use differential or not. I'd look at the complexity of the circuit with either option, and choose the one with fewer parts. (e.g. maybe differential would make the summing amp easier?). I also wonder whether the clock nulling circuits could be mangled into handling differential signaling.
On Jun 16, 2022, at 4:38 PM, Tom Wiltshire wrote:
> On 16 Jun 2022, at 23:11, Mike Bryant wrote:
>> You could add more BBDs in parallel and sum the outputs to reduce it again.
> I think this is what's referred to in the SAD1024 datasheet. That chip was actually a dual 512-stage device, and one suggestion was to use the two delay lines in parallel for reduced noise. I don't remember the details. Could be that simply summing the signals gives you a +6dB boost in the signal, but not so much in the noise, or it could be that it recommended a differential signal. Can't remember, sorry. I found an "Archer"-branded version of the datasheet here which shows various possibilities:
It seems strange that Archer shows the A' output as unused in the Serial configuration. They might not have aimed for high fidelity.
Similarly, the Parallel-multiplex operation shows both A' and B' outputs as unused.
The differential mixer seems to be entirely passive (at least ahead of the LM733).
>> If lowest clock speed is 20k, you really need to be filtering out everything about 10k.
> BBD datasheets generally recommend a conservative bandwidth of 1/3rd of the clock frequency, so 20K would be 6.67KHz. Poor, but much better than 3.3KHz!!
> I totally agree that 18KHz filtering with 20KHz clock is not realistic. No practical filter is that sharp.
Exactly. A circuit with ADC and DAC might incorporate a fancy digital filter with sharp 18k to 20k slope, but you're not building that with all analog components. The recommendation for 1/3 frequency allows fewer poles in the filter.
More information about the Synth-diy