[sdiy] Electrosmith Eurorack DSP platform

cheater cheater cheater00social at gmail.com
Fri Jan 28 19:57:22 CET 2022


So you're getting SNR that's like 16 bit at 48 kHz? Really? That's
really, truly impressive. I heard 1 bit DACs had some magic in them
but this really brings the point to bear.

On Fri, Jan 28, 2022 at 5:38 PM Eric Brombaugh via Synth-diy
<synth-diy at synth-diy.org> wrote:
>
> Because I'm using a sigma-delta approach to generating the PDM signals,
> there is some noise shaping going on and this system performs better
> than merely 12MHz/48kHz bits. I'm actually getting SNR that's
> approaching 16-bit performance.
>
> I found the FPGA-only ADC approach fiddly because it suffers from a lot
> of the same nonlinearity issues seen in the PDM DAC methods, is very
> sensitive to layout and component selection and requires a fair bit of
> post-filtering to reduce noise. It's kinda like the singing dog -
> amazing that it works but not what you'd call "good".
>
> Eric
>
> On 1/28/22 08:54, cheater cheater wrote:
> > Thanks. 12 MHz 1-bit is equivalent to 48 kHz at 8 bit. What do you
> > think would be necessary to bump this up to add 4 more bits? Seems
> > like using a 1-bit approach you'd need an FPGA able to output at 200
> > MHz... at which point layout becomes a problem. Do cost effective
> > FPGAs with that capability even exist? (never mind availability)
> >
> > What made the ADCs fiddly?
> >
> > On Fri, Jan 28, 2022 at 4:24 PM Eric Brombaugh via Synth-diy
> > <synth-diy at synth-diy.org> wrote:
> >>
> >> On 1/27/22 23:20, cheater cheater wrote:
> >>> On Thu, Jan 27, 2022 at 11:00 PM Eric Brombaugh via Synth-diy
> >>> <synth-diy at synth-diy.org> wrote:
> >>>>
> >>>> I was seeing harmonics down slightly better than 80dB with all the
> >>>> mitigation measures active. Without it was more like 60-65dB. Not quite
> >>>> as good as even an inexpensive sigma-delta I2S audio DAC, but a few SMT
> >>>> passive parts beat that for cost & simplicity and I2S DACs don't support
> >>>> 12MHz sample rates.
> >>>>
> >>>> Eric
> >>>
> >>> Thanks for the write-up, that's some great info. The github repository
> >>> was very helpful learning a bunch more about your approach. Really
> >>> nice of you to share, and those are some interesting results. I've had
> >>> a few questions if you don't mind.
> >>>
> >>> Regarding the results - really impressive. Is that 12 MHz at 1 bit?
> >>
> >> Yes.
> >>
> >>> What was the performance at DC?
> >>
> >> Didn't measure that - I don't see any reason it wouldn't be equivalent
> >> to the AC performance though. The back end is fully DC-coupled.
> >>
> >>> How many channels can you run on that ICE5LP4K? Assuming the data
> >>> comes from somewhere else and you want DC+Audio rates at enough bit
> >>> depth for a synth signal (pre-VCA/ENV which reduces required bit rate
> >>> but, say, it could be post filter, or any other module)
> >>
> >> This particular FPGA (iCE40UP5K in the QFN48 pkg) doesn't have a lot of
> >> I/O pins, so you'd be limited in that regard. Two pins / channel and
> >> roughly 32 uncommitted I/O so 16 chls. For more you could go to other
> >> families with larger pincounts - the cheapest ECP5 parts are available
> >> with 197 pins free, so 98 channels max, but then you'd likely be limited
> >> by the internal resources and would need to bump up to higher-capacity
> >> devices.
> >>
> >>> Do you think the same method could be used with a comparator or with a
> >>> saw oscillator to create a similarly inexpensive and good ADC?
> >>
> >> I've tried a few different types of FPGA-based ADCs - either with
> >> sigma-delta techniques or with PDM or charge-timing methods. So far I've
> >> found them to be fairly fiddly and not performing as well as inexpensive
> >> dedicated devices like the SPI ADC I used in the oscillator project. It
> >> may be possible to get good performance from such approaches but it's a
> >> trade-off in R&D time. For me it was simpler/easier to just buy something.
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