[sdiy] Electrosmith Eurorack DSP platform

cheater cheater cheater00social at gmail.com
Fri Jan 28 16:54:20 CET 2022

Thanks. 12 MHz 1-bit is equivalent to 48 kHz at 8 bit. What do you
think would be necessary to bump this up to add 4 more bits? Seems
like using a 1-bit approach you'd need an FPGA able to output at 200
MHz... at which point layout becomes a problem. Do cost effective
FPGAs with that capability even exist? (never mind availability)

What made the ADCs fiddly?

On Fri, Jan 28, 2022 at 4:24 PM Eric Brombaugh via Synth-diy
<synth-diy at synth-diy.org> wrote:
> On 1/27/22 23:20, cheater cheater wrote:
> > On Thu, Jan 27, 2022 at 11:00 PM Eric Brombaugh via Synth-diy
> > <synth-diy at synth-diy.org> wrote:
> >>
> >> I was seeing harmonics down slightly better than 80dB with all the
> >> mitigation measures active. Without it was more like 60-65dB. Not quite
> >> as good as even an inexpensive sigma-delta I2S audio DAC, but a few SMT
> >> passive parts beat that for cost & simplicity and I2S DACs don't support
> >> 12MHz sample rates.
> >>
> >> Eric
> >
> > Thanks for the write-up, that's some great info. The github repository
> > was very helpful learning a bunch more about your approach. Really
> > nice of you to share, and those are some interesting results. I've had
> > a few questions if you don't mind.
> >
> > Regarding the results - really impressive. Is that 12 MHz at 1 bit?
> Yes.
> > What was the performance at DC?
> Didn't measure that - I don't see any reason it wouldn't be equivalent
> to the AC performance though. The back end is fully DC-coupled.
> > How many channels can you run on that ICE5LP4K? Assuming the data
> > comes from somewhere else and you want DC+Audio rates at enough bit
> > depth for a synth signal (pre-VCA/ENV which reduces required bit rate
> > but, say, it could be post filter, or any other module)
> This particular FPGA (iCE40UP5K in the QFN48 pkg) doesn't have a lot of
> I/O pins, so you'd be limited in that regard. Two pins / channel and
> roughly 32 uncommitted I/O so 16 chls. For more you could go to other
> families with larger pincounts - the cheapest ECP5 parts are available
> with 197 pins free, so 98 channels max, but then you'd likely be limited
> by the internal resources and would need to bump up to higher-capacity
> devices.
> > Do you think the same method could be used with a comparator or with a
> > saw oscillator to create a similarly inexpensive and good ADC?
> I've tried a few different types of FPGA-based ADCs - either with
> sigma-delta techniques or with PDM or charge-timing methods. So far I've
> found them to be fairly fiddly and not performing as well as inexpensive
> dedicated devices like the SPI ADC I used in the oscillator project. It
> may be possible to get good performance from such approaches but it's a
> trade-off in R&D time. For me it was simpler/easier to just buy something.
> Eric
> >
> >> On 1/27/22 14:44, Mike Bryant wrote:
> >>> Thanks - that makes obvious sense now you mention it !!    P channel MOSFETs turn on very differently to N-channel - your method cancels this out.
> >>>
> >>> Can I ask what THD did you get to ?
> >>>
> >>>
> >>>
> >>> -----Original Message-----
> >>> From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of Eric Brombaugh via Synth-diy
> >>> Sent: 27 January 2022 21:30
> >>> To: synth-diy at synth-diy.org
> >>> Subject: Re: [sdiy] Electrosmith Eurorack DSP platform
> >>>
> >>> No secrets - this was a personal project to see how well it works.
> >>> Details are here:
> >>>
> >>> https://github.com/emeb/up5k_osc
> >>>
> >>> TL;DR on the differential PDM: The generic FPGA output drivers have a bit of asymmetry in the rise/fall times which can cause some low level harmonic distortion. There are a couple of techniques for dealing with this - 1) ensuring there's always a rise and fall in every output period, and 2) using differential signalling to cancel the asymmetry. I tried various combinations and saw improvements for both. Overall I'd estimate there was about a 15-20dB improvement in THD.
> >>>
> >>> The output filter consists of a passive RC on each differential leg, then feeding into a diff-amp with additional 1-pole filtering that outputs a unipolar signal at modular synth levels. Since the clock rate was so high and the baseband signal bandwidth fairly low in comparison there wasn't much need for fancier filtering than that.
> >>>
> >>> Eric
> >>>
> >>> On 1/27/22 13:51, Mike Bryant wrote:
> >>>> Ok Eric, you've got me on this one ! :-)  If it's not a trade secret, what does the output filter look like such that differential PDM is needed, and how much improvement does it give over single ended ?
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