[sdiy] Voltage vs current, was Low voltage synthesis?

Ingo Debus igg.debus at gmail.com
Tue Jan 18 15:09:58 CET 2022



> Am 18.01.2022 um 10:29 schrieb usenet at teply.info:
> 
> Even the mentioned arrangement of rectifier, filter cap and load hardly maters at the frequencies in question for reasonable dimensions. Sure, placing the load directly at the rectifier with the filter cap two metres away probably doesn't serve the purpose, but at a few dozen kilohertz it probably wouldn't make a huge difference.

This is not high frequency stuff. In my example we’re talking 100 Hz or 120 Hz (yes, it’s not a sine current, but that’s not the point here). There’s a nasty hum current from the rectifier to the filter cap, since both source and sink are very low impedance. There will always be some voltage drop across that line. When this wire/trace is shared with the wire/trace from the cap to the load you cannot get rid of that hum. On the other hand, when the wire/trace between rectifier and cap is not shared with anything else, that current cannot do any harm.

I don’t think I’m the only one who learned that lesson the hard way.🥵

Could even apply to DC scenarios. Imagine the CV input line to your VCO is shared with a line that carries a few amperes of DC current (or, more likely, the ground reference for the CV input).

Ingo
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