[sdiy] Issue with CD4024 Ripple Counter

John Staapel j.staapel at gmail.com
Tue Sep 21 18:38:13 CEST 2021


I had the same problems with 4013.  The problem was solved when i add a RC
(10k/33p) at the input of the 4013

Op ma 20 sep. 2021 om 22:12 schreef Magnus Danielson via Synth-diy <
synth-diy at synth-diy.org>:

> Tim,
>
> Put a logic chip as "driver" of the clock before the 4024, and then try
> having various wide loops of cables on the ground and VCC to see if that
> replicates the problem. Also try to jump a 100 nF ceramic across the driver.
>
> It is good to trigger the scope on the generator edge and then monitor the
> clock input and also the first DFF output.
>
> I still suspect ground-bounce.
>
> The "sharper" the "driver" is, the more ground-bounce I expect.
>
> Cheers,
> Magnus
> On 2021-09-20 19:11, Tim Stinchcombe wrote:
>
> Hi list,
>
>
> I give up.  I'm going to put all of this shit away and build a few more
>
> Freak Shifts.
>
> Well it seems overnight I've been a little overtaken by these events, but
> last night I started breadboarding a little test circuit for the sole TI
> CD4024BE that I have, to see if I could provoke it into misbehaving by
> gradually slowing down the clock edge rate, and having gotten so far decided
> to carry on regardless. Executive summary: I can't, on the face of it, it
> basically 'does exactly what it says on the tin'.
>
> My very simplistic circuit and scope traces attached.
>
> My signal generator is no great shakes, but the square wave it outputs has
> rise/fall times of 200ns, so plenty fast enough to not need to worry about
> further. Feed this (+/-5V signal) into a simple integrator with a 4k7
> resistor in series with a 500k trimpot (R1 just shown as 4k7 in the
> schematic); thus the output of this OA is slamming nearly rail-to-rail, and
> I can control the slew rate with the trimpot; 2nd OA scales this down by
> about half, so the signal swing is about 10V, and the resistor to -12V adds
> about 5V of offset so the signal is near enough unipolar 0-10V to
> comfortably feed the clock pin of the 4024. I'm triggering off of Q1 out of
> the 4024, and the 'divide by two' action is clearly seen.
>
> With the trimpot at zero, so R1 at just 4k7, traces annotated 'fast ...',
> the slew rate is about 6.5V per microsecond, i.e. not far off as good as a
> TL072 will go, and the clock falling edge time is less than 2us. The chip is
> clearly reacting to the falling edge of the clock, and there was absolutely
> no hint of the 'CLK' trace 'flipping' as it would have if the chip were
> occasionally responding to the rising edge of the input. (Note the changed
> vertical and timebase scalings for the 'zoom'ed trace.)
>
> With the pot at 500k+, traces 'slow ...', the situation remained exactly the
> same, apart from the more sluggish clock edge: the slew rate is now around
> 0.15V per microsecond, with a fall time of more than 70us.
>
> So on my sample size of 1, the chip seems to behave as it should, with no
> hint of any of the weirdness that David is/was experiencing in his circuit,
> suggesting that there is either some odd noise/coupling/whathaveyou issue in
> his PCB or it just so happens his TI chips are 'wonky' in some unspecified
> way.
>
> David: I'd be more than happy to stick one or more of your chips into this
> set-up if you felt inclined to post them to me, but it is so simple a means
> of testing it probably isn't worth the postage, i.e. you could probably just
> as well lash something very similar up yourself...?!
>
> Tim
> __________________________________________________________
> Tim Stinchcombe
>
> Cheltenham, Glos, UK
> email: tim102 at timstinchcombe.co.ukwww.timstinchcombe.co.uk
>
>
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