[sdiy] Issue with CD4024 Ripple Counter

Roman Sowa modular at go2.pl
Tue Sep 21 10:04:08 CEST 2021


inline...

W dniu 2021-09-21 o 03:18, David G Dixon via Synth-diy pisze:
> Just for Ss and Gs, I thought I'd show you my layout graphic for the ASR 
> board which has the clock circuit on it. Please see attached.  Note 
> that red traces are the +V rail and green traces are the GND rail (and 
> black traces are the -V rail).  The CLOCK pin of the 4024 is connected 
> to the light blue trace.

Your decoupling cap near 4024 has no effect. It takes too many maze 
traces for the cap to reach IC pins.
100k as pulldown on clock input after a diode seens low, may pick up 
interferences
TL072 used as comparator is not power-decoupled at all
It all may cause nice ringing on the edges, leading to multiple clocks


> Also, I should mention that when the ASR is being clocked by an external 
> LFO, the CD4024BE is clocking on the positive edge only.  However, when 
> the Manual clocking switch is used, the CD4024BE is clocking on both 
> edges.  The clock signal at the CLOCK pin looks identical in either 

If manual button clocks on push and release while clean external signal 
clocks on one edge, that just screams to me "the switch is bouncing". 
You don't have any debouncing in there. 1k/2n2 is nothing, this is 
microseconds, while switch may bounce during miliseconds. More effect on 
debouncing than this 1k/2n2 has the comparator's slew rate. Can you send 
us a scopeshot of the switch input and comparator output while it's 
pushed and released? Preferably with time base around 1us/div

But mosst of all why do you use 8-bit counter if all you need is 2 bits? 
Why not use IMHO more reliable 4 bit counters like 4516, 4518, 4520, 
4029? You could even use flip-flops like 4013 or 4027 for that.

Roman


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