[sdiy] Issue with CD4024 Ripple Counter

Roman Sowa modular at go2.pl
Mon Sep 20 10:57:45 CEST 2021


If it took just 2.5 hours to change layout, make new PCB, and solder it, 
then you're my hero.

By "stability capacitor" you mean a cap in negative feedback path? It's 
not something you'd like to see in a comparator at all. That would only 
slow down the slew rate. And if you say you've added decoupling to 4024 
"finally", that is a bit too late, as it should be the first thing to do.

I've had similar experience with another clock-is-everything module made 
by my friend. We tried to resolve it over email, trying weeks and weeks 
all sort of ideas, even the most bizare ones. When the last thing to try 
was using audiophile grade caps in 7805, directional oxygene free cables 
for power and marble stand for PCB, he finally came to visit me, and 
we've tackled the problem in roughly few hours. The reason was beyond 
unexpected - bad naming of nets in the project file. So it all looked 
good on paper, netcheck was OK, but hardware didn't work.
I'm not saying you've made a design error, but possibly something far 
away from obvious, which needs a look from other pair of eyes.
I can be that guy if you send me that F digital S.

Roman


W dniu 2021-09-20 o 04:38, David G Dixon via Synth-diy pisze:
> Thanks for all the tips, John.
> 
> I just spent the last 2.5 hours making a completely new PCB and stuffing it.
> I had to change the layout significantly to squeeze in a 1M hysteresis
> resistor.  I also added a 1nF stability capacitor on the comparator, since
> the simulation suggested that this would clean up some noise on the
> hysteresis output past the diode near ground (in the 10 to 20 mV range).
> Finally, I added a decoupling cap to the power pins of the 4024.
> 
> Results:  Disaster.  The MC14024 doesn't even work properly on the new
> board.
> 
> The clock signal at the 4024 Clock pin looks beautiful on the scope.  I see
> no oscillation at all, no fuzziness -- just a sharp and focused square wave
> with nice corners.
> 
> I give up.  I'm going to put all of this shit away and build a few more
> Freak Shifts.  At least I know how to build those, and I've got an ever
> growing pile of them to build.
> 
> 
> 
> -----Original Message-----
> From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of John
> Richetta via Synth-diy
> Sent: Sunday, September 19, 2021 5:07 PM
> To: David G Dixon via Synth-diy
> Subject: Re: [sdiy] Issue with CD4024 Ripple Counter
> 
> [CAUTION: Non-UBC Email]
> 
> Some suggestions:
> 
> 1. This circuit has a bit of complexity; simplify, to help narrow down the
> source of trouble. I'd suggest disconnecting the 10k resistor that feeds the
> circuit following the cd4024 clock output, and then perhaps also fully
> disconnecting the circuitry that follows from power (though my guess is that
> if this circuit is partly to blame, merely disconnecting it from the 4024
> clock will improve the situation). The thinking is that any oscillatory
> behavior in this circuit could well feed backward through the 10k resistor
> sufficiently to affect clocking of the cd4024.
> 
> 2. The power supply-derived reference voltage for your comparator has no
> bypassing, and certainly should.
> 
> 3. I won't lecture on using op amps as voltage comparators (I assume you've
> read the app notes about this), but will say that the circuit should
> undoubtedly have some hysteresis. As it is operated open loop, it will be
> maximally susceptible to noise (such as the unfiltered supply noise
> mentioned in point 2) during transitions. Lack of hysteresis is a common
> cause of problems with voltage comparator circuits. Occasionally, excessive
> hysteresis can be undesirable, but I doubt there will be any issue with it
> in this application (the main likely effect being ultra small clock edge
> delay).
> 
> I strongly doubt that problems as basic as you are having are due to
> manufacturer differences. A quick check of a 1979 RCA manual shows that
> their cd4024 versions also have hysteresis. The edges you are feeding the
> cd4024 may have spurious oscillations of a large enough magnitude to
> generate additional clocking when going through the transition zone (those
> extra transitions will often swing up and down a few or a dozen times, and
> so will clock any input, regardless of edge polarity).
> 
> HTH, -jar
> 
>> On Sep 19, 2021, at 01:29, David G Dixon via Synth-diy
> <synth-diy at synth-diy.org> wrote:
>>
>> The ASR clock circuit is attached to this email.
>>
>> The two switches are how I am simulating the ON-OFF-(ON) switch.  When
>> switch "1" is open, then the switch is in the OFF position.  When switch
> "1"
>> is closed, then switch "0" represents the momentary switch.  This
>> switch sends either 0V or 12V through a 1k resistor to the 2.2n debouncing
> cap.
>> The signal generator represents a signal plugged into the Clock input
>> jack (such as an LFO).  This comes in through a 10k resistor.  In this
>> way, the switch always has priority.  They are both fed through 10k
>> into the inverting input of the opamp comparator with a 100k resistor
>> to ground to provide a current path.  The threshold of the comparator
>> is set to a little less than 2V.  Hence, when the LFO signal rises
>> above this threshold, or when the momentary switch is pressed, the
> comparator output is negative.
>> The diode changes this to about 0V.  When the clock signal is less
>> than about 2V or the momentary switch is not pressed, then the
>> comparator output is positive.
>>
>> The output of the diode goes directly to the 4024 Clock pin.  This
>> will be either about 10V or about 0V, and the transitions will be
>> about 2 microseconds.  This is dropped to ground through a 100k
>> resistor to provide a current path.  This then goes through a 10k
>> resistor to a 5.1V zener to fix the level at 5V, then into a unity
>> gain inverter with a +5V level shift (-12V through 24k) to give a 5V
>> gate signal for the Gate output jack.  This signal will have the same
>> polarity as the incoming clock signal, even though the 4024 advances
>> on the negative edge.  This output can be used to gate an envelope for a
> filter, or whatever.
>>
>> If you see any obvious mistakes, I'd love to know about it.  As I
>> said, this circuit works perfectly with MC14024B, but CD4024B clocks on
> the wrong edge.
>>
>>
>>
>> -----Original Message-----
>> From: Synth-diy [mailto:synth-diy-bounces at synth-diy.org] On Behalf Of
>> m brandenberg
>> Sent: Saturday, September 18, 2021 12:04 PM
>> To: 'synth-diy mailing list'
>> Subject: Re: [sdiy] Issue with CD4024 Ripple Counter
>>
>> [CAUTION: Non-UBC Email]
>>
>>> On Sat, 18 Sep 2021, David G Dixon via Synth-diy wrote:
>>>
>>> Also, I would remind you that I set up a test rig on breadboard, with
>>> similar circuitry (an opamp comparator into a diode), and the 4024s
>>> either didn't work or looked real bad (lots of hash) even though the
>>> driving waveform is very clean.
>>
>> Sorry to belabor the point but the 'one diode' mention has made me
>> twitch twice now.  Is that one diode feeding into a passively pulled
>> up (or down) input or one diode into a floating node that might be
>> drifting around metastability?
>>
>>
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