[sdiy] Issue with CD4024 Ripple Counter

Phil Macphail phil.macphail at liivatera.com
Sat Sep 18 15:40:08 CEST 2021


How fast is the chip being clocked? Could it simply be the propagation delay through the chip happens to be half the clock-period?

Phil
Sent from my iPhone

> On 18. Sep 2021, at 16:34, Ben Stuyts <ben at stuyts.nl> wrote:
> 
> 
> 
>> On 18 Sep 2021, at 14:22, Phillip L Harbison <alvitar at xavax.com> wrote:
>> 
>> I would check for noise on the clock signal and  noise overall. If the clock has noise, you might consider first passing it through a gate with a Schmitt trigger. If the clock transition is slow you might consider passing it through a comparator configured with some hysteresis.
> 
> The 4024 already has schmitt-trigger input. (Not on the reset line though.) Datasheet says unlimited rise/fall time is allowed.
> 
> Comparing the CD4024 and MC14024 datasheets, I see quite a few timing differences. I noticed that the MC14024 is quite a bit slower: (@ 15V, Max) 4 Mhz vs 12 MHz.
> 
> Ben
> 
> 
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