[sdiy] CMOS mystery

[Colin Hinz]

Very much this.

With the additional caveat of "are you looking at the right datasheet"?

Interestingly, the 1980 RCA databook specifies a Schmitt-trigger input
for the clock and min/max rise/fall time is given as "unlimited". The
current TI datasheet for their CD4024BE seems to have the exact same
table of specs. (Not too surprisingly, as TI bought the 4000-CMOS line
from Intersil who got it from RCA back in the 1980s.)

But wait! The 1977 Fairchild databook does not specify a Schmitt-trigger
input and thus the AC Characteristics table does provide "recommended"
rise/fall times.

The 1984 Motorola databook shows a Schmitt-trigger input yet specifies
maximum rise/fall times. Go figure!

So, be sure to match your datasheet to the devices you are using....
Fortunately, having a few thousand databooks at one's disposal only
requires a USB "thumb drive" instead of a moderately large room.

Getting back to the original problem, I need to ask: how do the
propagation delays differ between devices?

Also, the chip manufacturers advise against using the internal diodes
for voltage conditioning. Clamping the input voltage during an ESD
event is different than clamping the input voltage for 50% of the
circuit's operation.

- Colin

On Sat, 7 Jul 2018, René Schmitz wrote:

> Hi David and all,
>
> I would ensure that the clock has fast enough rise time. "Slow" 
> waveforms sometimes fail to trigger flip flops (and counters made from 
> them). If needed use an schmitt trigger gate to speed up the rise time.
>
> Best,
>  René
>
> On 07.07.2018 02:16, David G Dixon wrote:
>> Hey Team,
>> 
>> So, just a quick update on the fifth generator situation...
>> 
>> Today, I took my old PCB and tried the two different brands of 4024 counter
>> -- one that worked and the one that didn't.  On this PCB, I'm creating the
>> 1/3 duty cycle pulse wave from the triangle with an LM311 comparator 
> between
>> 0V and +5V, so the resulting pulse wave will be exactly 0 to 5V.
>> 
>> The result:  Exactly the same.  The CD4024BCN chip worked, and the CD4024BE
>> chip did not work.
>> 
>> Then I realized my mistake: The square wave I'm sending to the 4024
>> counter's CLK input is the VCO's output square wave, which is 10Vpp, -5V to
>> +5V.  D'Oh!  Of course, the input diode on the 4024 clock input is limiting
>> the negative swing to one diode drop below 0V, but there is probably a fair
>> bit of current flowing through that diode (about 5mA, I'd guess, given the
>> 1k output resistor on the square wave output).
>> 
>> So, I kludged on a 10k resistor from the square wave, a 5.1V zener to
>> ground, and a 30k resistor to +15V.  This made the CLK input more or less
>> exactly 0 to 5V.
>> 
>> The result:  No change.  The CD4024BE chip still does not work, but the
>> other ones do.  I've come to the conclusion that these CD4024BE chips are
>> just defective somehow.  The funny thing is that I'm only using the Q1
>> output, and it looks fine on the scope, but it obviously is doing something
>> very weird to the subsequent logic gates.
>> 
>> I'm still stumped, but I've learned a couple of important lessons.
>> 
>> So, I'm thinking that it would have been OK just to put the 10k
>> current-limiting resistor in between the raw square wave output and the 
> 4024
>> CLK input, and let the on-board protection diode limit the voltage, with a
>> paltry 500uA of current flowing through it, which isn't going to hurt
>> anything.  Am I thinking about this correctly, or is it just a whole lot
>> harder and more sophisticated than my tiny brain is capable of conceiving?

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