[sdiy] New SPI SRAM

[Tom Wiltshire]

> On 15 Jul 2018, at 23:22, Richie Burnett <rburnett at richieburnett.co.uk> wrote:
> 
>> Excellent! Someone was asking me about how to increase the delay length for my dsPIC Digidelay project the other day, and that would be a simple solution.
> 
> Thought it might be good for that.  It's currently available in SOIC, TSSOP and BGA, so no DIP yet, but not hard to put SOIC down on an adapter board.
> 
>> The current design uses two 23LC1024’s for 4 seconds of delay memory at 32KHz. That would push it out to 16 seconds without a lot of other changes beyond tweaking the addressing (e.g. no extra chip select lines or other hardware changes).
> 
> The part that I posted the datasheet link for has some wait states.  So it's not quite the same as the 23LC1024.  Looking at the timing diagram, it's almost the same, except you don't start getting the data until 8 SPI clock cycles (one byte) after you finish sending it the address.  I think that this is to allow for the access time of the internal RAM given that the SPI clock can be as high as 45MHz.  It essentially can't read in the last bit of the address, then find that location in RAM, read it's contents and start presenting that data back to you on the very next SPI clock cycle.  It needs a little RAM access time.  The one byte "read latency" isn't a big deal for block transfers, but might be a significant bottleneck for random single-byte reads.
> 
> -Richie, 

Very interesting, thanks. I made sure to use block reads to keep the speed up anyway, so I don’t think it’s a deal-breaker. One block worked out as 2 msecs of samples - not a huge amount. That became the smallest “unit of time” in the design. And I’m pretty sure the SPI clock was nothing like that fast, so pushing that up a bit would probably more than compensate.

T.

==================
       Electric Druid
Synth & Stompbox DIY
==================