[sdiy] Modern codecs in variable-rate digital delay?

Steve Lenham steve at bendentech.co.uk
Thu Mar 23 13:06:39 CET 2017


On 22/03/2017 20:05, Tom Wiltshire wrote:
> Another potential problem would
> be building a VC oscillator/clock that could reach the required
> speeds, since many chips seem to need master clocks of Fs x64 or
> more. That's getting up into the ten+ MHz range.

Have a look at the Cirrus CS2000 family of clock synthesizers. They can 
take a low frequency clock and generate a stable output at a high 
multiple of that frequency.

The bandwidth of the PLL filter is programmable. Although for many 
applications this would be set low to remove as much ripple/jitter as 
possible, when set to max it will track modulation rates up to 128Hz 
without attenuation.

I used one to generate the master clock for a digital audio system from 
an incoming Word Clock signal, multiplying a 44.1-192kHz signal by x256, 
and it worked well.

Cheers,

Steve L.
Benden Sound Technology



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