[sdiy] Analysis of the TB-303 CPU timing

Colin f colin at colinfraser.com
Thu Mar 16 16:28:27 CET 2017


> While I was working on a reimplementation another guy over at the RE-303
> forum got this image working running on my AVR based CPU hardware using
> the MAME code.
> It runs surprisingly good, but even with a 20MHz clock it has timing
problems.
> There is a noticeable lag between clock input and reaction. About 1/2 to
> 3/4 of a whole clock cycle at medium tempo and the gate off latency seems
> to be more in the 10ms range than the 2.4ms I measured on the original
CPU.

You don't need to run it in real-time to use it to generate precise
measurements of the jitter & latency you would get from the real machine.
Did anyone disassemble the hex file to readable text ?

Cheers,
Colin f






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