[sdiy] Analysis of the TB-303 CPU timing
elfenjunge at gmx.net
Wed Mar 15 18:10:35 CET 2017
regarding 2) I still have all the analyzer data saved for later inspection.
I went for small zoomable graphics in favor of a nice looking layout.
That's probably the non academic approach.
In the end I was too lazy to export all the measurements as CSV and
replot them in something like gnuplot as vector images.
For printing I think a dark background isn't too good either.
regarding 3) I try to find out the best way to generate some statistical
descriptions from the data I have. Never done this before.
I basically just thought writing something like a paper is probably more
useful than just uploading a huge dump of logic analyzer data.
But it's always good to learn something and get some feedback. Much
I never wrote a paper before besides my diploma thesis years ago and it
was fun to dust off my LaTeX skills again.
I already implemented most of my findings in the replacement CPU I'm
developing. The lag of the gate signal is already switchable, but not
the interplay of the clocks which is the more interesting part imho. So
maybe I can make some A/B testing in a few days when realtime switching
to a pin change interrupt for the tempo clock is implemented.. Turning
off the 1ms on and the 2.4ms off lag makes no big difference to my
Am 15.03.2017 um 17:13 schrieb Bruno Afonso:
> Thanks for this work Julian, very interesting. A couple of notes:
> 1) For things like ISR and DAC, just write them out the first time
> they appear ,i.e.: "interrupt service routine (ISR) " and then just
> use ISR subsequently. This way for someone reading linearly from the
> beginning everything is obvious.
> 2) some figures small and thus hard to see without zooming, maybe crop
> the pics to the part that matter or that is critical to the point
> you're making. Think about someone printing it, can they still see
> what you'd like them to? If you can't crop to show the point you are
> trying to make, maybe it's superfluous.
> 3) you mention jitter several times but there is no statistical
> description of the phenomena (mean, std dev, etc) or even a graphic
> depiction such as an histogram. Without this it's hard for the reader
> to see how relevant it may or not be.
> The article hinges on how interesting the 303 is due to the interplay
> of clocks. You do not mention where you'd like to go next or what
> would be useful to further explore. This is normally included in order
> to share things that in your mind are important and left to uncover. A
> younger brave soul may just try to pursue this, what a nice side
> effect! Personally, I feel it would be cool to simulate the clock
> interplay to reproduce obseved experimental data and then explore the
> space in order to get it more tight or more loose. Would it have a big
> impact on sound and experience? Would people care or notice if they
> used a much tighter 303 clock wise?
> On Wed, Mar 15, 2017 at 11:14 AM Julian Schmidt <elfenjunge at gmx.net
> <mailto:elfenjunge at gmx.net>> wrote:
> I'm currently working on a TB-303 replacement CPU for the RE-303
> Since there is not too much information available, and a lot of
> speculations are running wild on the net, I tried to clear things
> up a bit.
> Someone from the RE-303 forums loaned me an original CPU and I
> hooked it
> up to a logic analyzer and did some extensive testing and measurement
> I summed up my findings in a short paper available here:
> I have to admit, a lot of it is definitely from the "hear the fleas
> cough" category, as we say in Germany, but at least we now have data
> coming from a real CPU.
> Comments are welcome. I'm a bit rusty in writing proper papers ;)
> Synth-diy mailing list
> Synth-diy at synth-diy.org <mailto:Synth-diy at synth-diy.org>
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the Synth-diy