[sdiy] New SID Chips?
nvawter at media.mit.edu
Fri Apr 22 23:07:18 CEST 2016
FWIW, I'm sure a good deal of the SID filter magic is in the multiplier
and adder stages...
It's a standard SVF with the the integrators and gain stages (for VCF)
implemented in single-ended MOS.
If you were to fiddle with non-linear implementations of the two-input
MOS adder and the two-input multiplier,
you'd find the sweet spots and possibly even some more interesting
I think a decent sample rate would let you do this in DSP just fine...
e.g. an STM32F4 @168 MHz or a PICMZ @200 MHz both have FPUs. If you
could get the operation to about 168 operations, you could run the
algorithm at 1MHz, which is about 25x44kHz. IIRC, the digital limit of
MOS at the time of the C64/MOS6581 was about 4-5 MHz, so there's
probably not much signal activity above 1 MHz anyway :)
My main beef with the SID is that all four waveforms have the same
amplitude... the triangle is sooo quiet
compared to the pulse!
And I think more of the SID magic comes from its other features, like
the sync waveform and even more from the
overlap of programming and composition that it inspired... Making
synced wavetables is great. I love my SIDstation so much :) It makes
it so easy.
On 2016-04-22 16:03, Eric Brombaugh wrote:
> On 04/22/2016 12:51 PM, Gordonjcp wrote:
>> If you were doing it on an FPGA you'd just implement a digital filter,
>> which would sound better anyway.
> True, but goodness are you missing the point here. :)
> People *love* the imperfections in the SID analog implementation.
> Recreating the digital logic is cake, but duplicating the non-ideal
> behavior of the original lo-tek circuits will probably take the
> majority of the reverse engineering time. Anything less and the result
> will be panned as a failure by the true believers.
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