[sdiy] 1-bit ADC for audio/audio delay

David Moylan dave at westphila.net
Thu Apr 14 02:41:55 CEST 2016

Ah, reviewing the schematic and article, this is a delta modulator not a 
sigma delta modulator.  So none of the information I gave is really 
appropriate.  Noise shaping is not a feature of Delta modulation, only 
SigmaDelta modulation, so you'd only get 1 extra equivalent bit per 
doubling of sample frequency.

Let's be generous and say your oversampling ratio is 10 times over 44K. 
  That's only ~3.3 doublings x 1 bits per doubling is going to give you 
an equivalent of about 4.3 bits.  Obviously that's not going to sound 
too great.

It may be worthwhile if you're breadboarding this to sum the input and 
the feedback into a true integrator before the comparator to form a 
first order SigmaDelta modulator to take advantage of noise shaping and 
get 1.5 equivalent bits per doubling.  Same sampling frequency would get 
you to about 6 bits (still crap but improving!).  If you can push to 1 
Mhz you'd be closing in on 8 bits!  Of course, on a breadboard higher 
frequencies can start to be problematic.

For the integrator, using the 1/f = RC method would suggest dropping the 
100K resistor down to ~470 for 440kHz sampling rate.

One symptom that will tell you your R or C is too small for the 
SigmaDelta case is that it will oscillate.  And overloading the 
integrator usually sounds like aliasing at lower sample rates, but I'm 
not sure if that will hold at these higher sampling rates.  The above 
calculation is a good starting point if you go this route.

The references to 64x oversampling is probably referencing higher order 
sigma delta modulators, not simple delta modulators...

Dave Moylan

On 04/13/2016 06:53 PM, Tom Wiltshire wrote:
> Hi Brian,
> No, you're right, it's pretty vague. The article gives values of "RX, CX (typically 10 Ω, and 0.01 µF)"' and says only "The circuit, run at a clock rate of 100 kHz, will give high-quality voice reproduction. Higher clock rates will provide near-CD quality." But doesn't go as far as actually saying *how* high or *what* exactly!
> I've been experimenting with frequencies in the several-hundred-kilohetrz range, about 250-400KHz. My best results don't match the RC values they give at all. At such low frequencies, I'm  not expecting miracles, but it still seems like other people have had better results than I've managed yet. Everyone says x64 is a reasonable oversampling ratio for 1-bit convertors - that implies around 3MHz for decent audio - a long way up from my current set-up.
> But this question of how the integrator values and the clock frequency should be related remains to be answered, it seems to me.
> Thanks,
> Tom
> On 13 Apr 2016, at 20:21, rsdio at audiobanshee.com wrote:
>> Tom,
>> I noticed that the article doesn't specify the clock frequency that matches the RC values given. What clock frequency are you using? As Dave says, the correct values are very dependent upon the frequency.
>> Brian
>> On Apr 12, 2016, at 2:55 PM, David Moylan <dave at westphila.net> wrote:
>>> There are some issues with sigma delta to remember:
>>> On a 1 bit converter it takes a whole lot of oversampling to achieve a high equivalent bit depth.  If I recall a single order integrator gives optimum 1.5 bits for every doubling of frequency, second order is 2.5. Somebody google that for me... :)
>>> The RC filter in the feedback path determines the transition frequency of the noise shaping.  The thought then would be that you want that transition frequency to be as high as possible so that the noise is shaped to boost frequencies way beyond the cutoff frequency of the reconstruction filter but there are other concerns.  If the RC time constant is too small you can saturate the filter.  I saw a reference that said optimum RC (for a true integrator) is 1/RC = f, where f is the sampling frequency, but was unable to see the original source which is an expensive text book:
>>> Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance Limits and Robust Implementations, Gerfers & Ortmanns
>>> In my experiments I felt like I was still getting saturation with those values and increased the capacitor value a bit, and also degraded the maximum gain of my integrator.
>>> On 04/11/2016 06:12 PM, Tom Wiltshire wrote:
>>>> One further thing: I couldn't get the RC values provided in the article to work at all. They suggest "The output of the comparator (Point B) is integrated by Rx, Cx (typically 10 Ω, and 0.01 µF)" but I finished up using 100K and 4n7 to get a better result. This is so different that something fishy is going on.
>>>> On 11 Apr 2016, at 22:59, Tom Wiltshire <tom at electricdruid.net> wrote:
>>>>> 	http://electronicdesign.com/analog/low-cost-audio-delay-line-uses-1-bit-adc
>>>>> Everyone likes a simple audio delay, right? And you can't get much simpler for a digital delay than that, so I thought it'd be worth playing with. Note that the image in the original article has an error and takes the feedback from the wrong place, after the comparator instead of after the latch. My image is corrected.
>>>>> Now, the circuit works well enough, but it doesn't work as well as I'd expected. For now, I've got no shift register. I'm just doing the ADC, then feeding the bits out again so I can compare input and output signals for quality. I've done lots of experiments with PWM audio output, and I've got better results than I'm getting out of this. And this *should* work better than PWM, since the "PDM" output it produces should have less jitter than a PWM output would.
>>>>> In practice, it's quiet with no signal going in (what would be the worst case for PWM - the midpoint voltage) but when it gets a signal, there's a substantial amount of background white(ish) noise. Now, I understand that it's never going to be hi-fi (that's not the point) but I don't understand why I should get more noise with a signal than without.
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