[sdiy] Typical ESR of different capacitors

Tim Stinchcombe tim102 at tstinchcombe.freeserve.co.uk
Thu Sep 2 22:11:32 CEST 2010

Hi Antti,

> > least one could model it in SPICE). And in fact I was pretty certain
> > that our problem was caused by the ESR being _too low_! In 
> the end we
> National Semiconductor appnote 1148 warns against this. 

The problem I found with some of the app notes was that they took way too
simplistic an approach. You only need to add in another big cap or two on
the output, and you get poles and zeroes everywhere, as the ESR of one cap
interacts with the capacitance of another, and the regulator o/p impedance
forms poles with the caps and so on and so forth - the simple approach then
seems to go straight out of the window, which is why (I felt) we needed more
information so that we could effectively simulate the set-up, and then have
an educated guess at what effect the ESRs of the caps were having, rather
than a wild ass guess we ended up using.

Anyhow, that 1148 ap note one you mention was one I was using too - here are
some of the others:






Tim Stinchcombe 

Cheltenham, Glos, UK
email: tim102 at tstinchcombe.freeserve.co.uk

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