[sdiy] DsPIC timer issue when used as DCO!

karl dalen dalenkarl at yahoo.se
Wed Dec 16 23:17:43 CET 2009

--- Den ons 2009-12-16 skrev Tom Wiltshire <tom at electricdruid.net>:

> That's an interesting question, Eric.
> Is the choice of the MC series significant or not? It
> doesn't allow 32-bit PWM outputs, does it?

This was my initial approach from the beginning since DSI used
the MC variant i assumed things to quick i suppose , it seams that
there are some difference's among the dspic families..

> Dave is right about the hard sync - it's straightforward to
> do. When the reset interrupt for one DCO occurs, it can
> simply reset the other DCO too.

yes, i was mentally toying in the same direction.

> I would be surprised if DSI used the two timers and OCx
> output in the way you suggest, Karl, although it *might* be
> possible to do so. It sounds awkward to me, and the part of
> my brain that tries to keep my programming tidy is shouting
> "No! no! Don't go there!" at me. I haven't got a specific
> reason why or problem with it, but my instincts tell me that
> they wouldn't have done it that way. 

Well, if MC variant are the same as the GP what else options
do DSI have?

>The only reason to do it is to avoid the use of an interrupt, 
>and I don't see why  the use of an interrupt is to be avoided particularly.

ISR for the hardsync you mean? But isnt that just successive writes
to TMR1 and then a write to TMR2 no matter if the timers are concatenated
internally or externally?

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