[sdiy] DsPIC timer issue when used as DCO!

Dave Manley dlmanley at sonic.net
Fri Dec 11 17:11:27 CET 2009

Oh yeah - agree the slow drift is AC coupling somewhere.

Dave Smith lives a short distance from me - if he wants to make the two 
or three line code change, I'll bring the beer and we can watch it work 
properly.  No need to send a Prophet or the code!



Dave Manley wrote:
> My final comments on this Friday morning!
> 1. the dac value is updated, increasing the current drive, causing the 
> cap to charge and saturate
> 2. the waveshaper sweeps to the value caused by the max voltage on the 
> cap - up and then back down
> 3. the timer has period was N, was changed to M<N, when the TMR reg 
> value was greater than M, causing the rollover - no ISR involved per 
> my earlier speculation
> 4. finally the timer wraps and resets the cap and it starts working 
> correctly
> The way to fix it: write the TMR register to a value just less than N, 
> NOP if needed to wait for TMR to hit the max value of N and resets the 
> cap.  Now write the new value M.  This will cause the output waveform 
> to change from f1 to f2 almost instantly.
> 5. I'm guessing they are using the output compare logic to generate 
> the reset pulse.  There's no reason not to, and it removes the need 
> for the ISR.  The output compare registers don't need to be changed 
> when updating the period register.  Set the output compare to generate 
> the reset pulse during the early counts of the timer.  As long as the 
> output compare toggles well before the minimum period value required 
> for the highest supported frequency (which it must) then everything 
> works.
> I like Colin's idea for replacing the whole thing!
> -Dave
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