[sdiy] Tap Tempo LFO

Eric Brombaugh ebrombaugh1 at cox.net
Wed Dec 9 02:35:20 CET 2009

Interesting discussion.

Using a general-purpose MCU to create a clock for a BBD is probably out 
of the question for most garden-variety processors. While a lot of them 
have divider-based timing generators built-in, the high-frequency 
resolution is probably not adequate to support decent timing & frequency 
control at the rates needed to clock a BBD.

There is one part I can think of that might work for this:


A little ARM processor with a built-in DDS that can run up to 21MHz with 
0.005Hz resolution. Costs a bit more than you probably want to spend 
though, and might need some fairly careful layout. OTOH, it's got decent 
ADC on-chip and could make a very interesting Digital VCO besides its 
application as a BBD clock.

Might be able to build a home-made DDS with an external CPLD though - 
that would be a bit cheaper if you picked the right parts. Alternatively 
you could use a cheap RF PLL chip (usually programmed via SPI) - those 
would give great jitter-free clocks in a single external chip. They're 
also doing some amazing things with programmable CMOS oscillators these 
days that give wide frequency ranges in very small & inexpensive parts - 
check out Silicon Labs 'Any-Rate' line for example.


On 12/08/2009 05:56 PM, Tom Wiltshire wrote:
> Mike,
> Thanks for the kind words.
> There are two reasons why what you suggest isn't possible.
> One is that the output sample rate simply isn't high enough. It's only
> 19.5KHz, which rules out any frequency above almost 10K even in theory.
> In practice, you wouldn't get much above 2 or 3KHz. The sort of output
> rates you're talking about are 100's of KHz.
> Secondly, the part of this that is 'tap tempo' is the LFO frequency,
> e.g. the rate of change of some parameter. This is not the same as the
> delay time being tap tempo. For this, you need to do a different sum
> involving the clock rate of the delay and the length.
> It's a damn pity that it isn't do-able though, because this is something
> I've wondered about enough times myself. If you could get a uP to
> generate a clock signal for a BBD directly, you be able to do tap-tempo
> delays, flangers, chorus and the like, and you'd only need the uP and
> the delay line. None of that messing about with clock chips or VCOs
> driven by LFOs.
> Still, BBDs suck, so it doesn't matter, right? ;)
> T.
> On 8 Dec 2009, at 20:44, Mike Beauchamp wrote:
>> Tom, First of all this is absolutely brilliant.
>> Secondly, I'm wondering how easy it would be to reprogram it to have a
>> 1:4096 tap:clock ratio? (if that makes any sense).
>> The reason I ask is that I'd really like to use this to add a
>> tap-tempo to an analog delay...
>> The actual wave output could remain 1:1, just the clock output needs
>> to be 1:4096. Then I could use the wave output to drive an indicator
>> LED for example.
>> --
>> Mike Beauchamp
>> mobile: +64 21 0 AS I BIKE (2742453)
>> home: +64 4 801 8304
>> work: +64 4 915 4068
>> http://mikebeauchamp.com
>> http://therevox.com
>> On Wed, Dec 9, 2009 at 12:40 AM, Tom Wiltshire <tom at electricdruid.net>
>> wrote:
>>> Hi All,
>>> I've mentioned my Tap Tempo LFO project here before. The difference this
>>> time is that I've actually finished it!
>>> Details are online:
>>> http://www.electricdruid.com/index.php?page=projects.taplfo
>>> There are example circuit diagrams for a tap tempo LFO, tap tempo
>>> sequencer
>>> clock, and tap tempo tremolo, plus, a datasheet, code, etc. Any
>>> questions,
>>> please ask.
>>> If you're into PIC programming or know someone who is, you can get
>>> code from
>>> the site. If not, I'll be trying to sort chips out soon, and if I can
>>> persuade Steve Daniels that this is a good idea, you might be able to
>>> buy
>>> programmed chips from Small Bear. He did show some interest, but
>>> we'll see
>>> whether it's really worth his while. I hope so.
>>> Thanks,
>>> Tom
>>> _______________________________________________
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