[sdiy] VCO waveform logic selection

harrybissell at wowway.com harrybissell at wowway.com
Wed Sep 12 19:08:16 CEST 2007

No that's not it...

Normally a 4000 series CMOS logic chip works on a single supply.

The Pro V circuit takes advantage of two things...

1)  The voltage divider action when the switch is on.

With the 100K in series (effectively) with the input, the input
protection diodes can easily uhhh... protect the input against a
negative swing when the input is off

2) Biasing the Vss supply (normally ground) one diode drop negative
allows a swing of -0.7V at the input. Fortunately this negative bias
is so small that the normal logic level signals can be used. The input
control might be 0-15V and the chip input would trip at 1/2 the difference
between Vdd and Vss... so the loss of that -0.7 volts has no effect except to
change the 'noise immunity' a tiny bit.

The Pro V used the 4016 analog switches in many places, which have only two
power supply pins (the 4051 (52,53) have three pins to allow the logic levels
to be ground referenced

H^) harry

On Wed, 12 Sep 2007 09:06:31 -0700, Dave Manley wrote
> >> Are the protection diodes built into the device inadequate for this 
> >> purpose?
> > 
> > Those diodes delimit the amplitude to +-0.6V around GND, while the input 
> > protectors do clamp against Vcc and GND. Delimiting the swing at the 
> > open switch does reduce the risk of capacitive crosstalk.
> > 
> > Cheers,
> >   René
> Ahhh, thank you...I see I completely missed the point.  The open 
> switch is not connected to the virtual ground, and so it swings with 
> the input signal.  The diode clamps to ground limit this swing.
> The follow-up question then is with a typical +/-5V swing on the 
> unconnected input how much of that signal appears in the output?
> -Dave
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Harry Bissell & Nora Abdullah 4eva

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