[sdiy] VCO waveform logic selection

Ingo Debus debus at cityweb.de
Tue Sep 11 21:16:39 CEST 2007


Am 11.09.2007 um 11:12 schrieb jbv:

> would some analog mux like the 4051 do, if its power supply is set
> to +-7.5V ? If yes, how to handle logic selection signals, especially
> if they're generated by 3V logic uC ?

Quote from the CD4051 datasheet (Nat Semi, first page):
"Control of analog signals
up to 15Vp-p can be achieved by digital signal amplitudes of
3-15V. For example, if VDD=5V, VSSe0V and VEE=-5V,
analog signals from -5V to +5V can be controlled by digital
inputs of 0-5V."

WRT handling a 3V logic high level, some 3V-microprocessors are "5V- 
tolerant", i.e. although the supply voltage is 3V, outputs may be  
pulled up to 5V with an external pullup resistor.


Magnus wrote:
> However, if there is leakage through the 4051, then it is pretty much
> undampend.

There are variants of the 4051 with much less leakage than the  
standard CD4051 (from Maxim for instance). However, according to  
Maxim's datasheet, almost all leakage is caused by the protection  
diodes, thus it's a leakage current from the analog I/Os to GND or  
VCC. This won't cause signal bleedthru.
If signal bleedthru is a concern, then in this case probably only if  
the output is to be turned off completely (who cares about a tiny  
amount of square wave mixed into the sawtooth?). In this case, if  
there's an input of the multiplexer left, it can be switched to ground.

Ingo



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