Fast analog sw. as VC resistor

brad sanders radioactive at geocities.com
Thu Jan 16 09:35:57 CET 1997


>I did some more piddling around with these 4053 switching circuits...

You REALLY need to get some DG samples! What's the rdsON of the 4053?
One K or so? And the tON and tOFF? 

Those endpoints are driven by these benchmarks. The faster you can
turn a switch on or off, the faster and/or more accurately you can
clock them. For example, most of the Maxim DG switches switch on/off
in around 150nS - tops. Add to this the fact they'll swing rail to
rail, rds ON of about 30 Ohms, fully protected inputs, etc - they're
just WAY better'n them old-fashion CMOS things. Yes, they're more
pricey - but not TOO pricey (and anyway, the first two are free!)

>I tried several configurations of an output voltage divider using the
>bipolar supply: between GND and +12V through 100K resistors like above,
>between -12V and GND through 100K's and between -12V and +12 V through
>100K's. These all seemed to work fine. However, when I tried between +12V
>and -12V WITHOUT the other 100K resistors, I toasted my 4053! I'm not sure
>what's causing this: too much current passing through the switch or what.

Sounds like it. Remember: the way you've wired that divider, at each
transition BOTH contacts are going to be closed - ACROSS the power
supply! The "short circuit" is a trait inherent to ALL CMOS, not just
analog switches. With these older technologies and their slower
risetimes, we're talking a LONG time (on a chip level, anyway) - maybe
even 100nS or more!

Figure 100KHz (10uS)/100nS ON time for two switches "shorting" across
24 volts- approx a 2% duty cycle! (remember: two state transitions/Hz)
Did that chip get pretty durn hot?

Again, faster processes will help this; so will NOT connecting both
sides of the switch to opposing (high) voltages WITHOUT current
limiting resistors. 

Oh - if I properly understand what you're describing, those "glitches"
you're getting at the ends are going to be there, to a degree, no
matter what. Think about it: the logic and switching circuitry will
have finite rise/fall times. Propogation delay isn't so terrible, so
long as it's more or less equal rise/fall - but the initial lag, and
rise/fall time, will limit minimum and maximjum duty cycle (no big
news there: look at any synth with 5%-95% duty cycle on the pulse).

So, you need to plan for this. You'll ALWAYS get that "foldback" you
noticed as you approach zero or infinite duty cycle (actually, they're
the same thing, if you think about it: both result in "zero Hz")
Minimizing the switching times will maximize your linear range.

If you'll notice the input dividers on my ADSR gen, for example, I use
a 5V reference to the comparators AND assume a 5V signal (like the 10V
trigger divided by two 10K resistors). I'm all but certain I'll have
to change one resistor - or divide the 5VDC down to 4.5VDC or
something, just to prevent the control voltages from creating such a
"zero Hz" condition. When I get it wired up I'll play with this to
maximize my linear range (Spice? What's Spice? Spice gives me
heartburn). 


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