DIY Digital Scanning Keyboard (Cor Blimey!)

Clive Jones CJones at sni.co.uk
Mon Feb 19 23:54:00 CET 1996


Okay then - since Digisound nicked my Digital note generator design and   
I'm sueing the pants off them (just kidding), I've just come up with   
(literally!) a digital keyboard which is self scanning and requires no uP   
overhead. The design outputs an 8 bit data word representing the keys   
"down", no key down=word value of 00h, it's all theory as I do more of   
this than wave a soldering iron around nowadays, but, I see no reason why   
this should'nt work.

1 - Build a clock circuit around 500khz, this should scan each key on a   
64 (yep, I know it should be 61 but 8x8 - yes?) keyboard every 7.8Khz,   
plenty of time! The keyboard scan will occur every *other* event, the   
non-keyboard scan event time or "blanking" period will be used for the   
interface device to access the scan results from RAM e.g scan keyboard,   
rest (one full keyboard scan event time - read results), scan   
keyboard.....

2 - Build an 8x8 scanning circuit, use two 4017 johnson counters - 1 to   
drive the *rows* and 1 to drive the *columns* - you'll need to buffer the   
4017 outputs to drive enough current through the key contacts to get a   
clean reading on return - use transistors or open collector gates with   
pull-ups (my favourite). The 555 clock pulse is fed into the *row* 4017   
counter clock input via a current limiting resistor, when the count   
reaches Q8 link this output to the clock input of the 4017 *column*   
counter, so, for every *row* completed (Q0-Q7) it clocks the next   
*column* on Q8 going high. When the column count is complete (Q0-Q7) wire   
Q8 of *this* (column) counter  to a flip-flop who's output DISABLES THE   
BUFFERS/DRIVERS but allows the 4017's to output pulses on it's "Q" output   
pins.  This means that for one complete "blanking" period no current is   
sent through the matrix (although the count continues) before the   
flip-flop is toggled *again* (triggered by Q8 of the column counter on   
the next pass) and the circuit outputs current to the matrix once more.   
The 8 return lines from the matrix are fed into an 8 input nand gate that   
switches state *every* time the circuit detects a key down and gets a   
positive voltage back from the matrix, use current limiting and or   
potential dividers to get the inputs down to the correct level for the   
gate to prevent it going into orbit. The output of this nand gate could   
be used to trigger a gate voltage generator (you couldn't do it directly   
as it's "on" pulse would be so short you couldn't trigger an EG with   
it!).

Okay following so far?

3 - Addressing the memory: Whilst all this is going on the 555 is also   
clocking an 8-bit binary up-counter which is wired to the address lines   
A0-A5 (we only require 6 bits to address 64 different memory locations)   
of a 6116 CMOS RAM, were not interested in anything other than static RAM   
because of memory "refresh" and other nasties that we don't want to deal   
with. All unused 6116 address lines are tied to ground, the write signal   
is derived from the 555 clock pulse which is inverted (if write is active   
*low* otherwise it's okay), the outputs of this 8 bit counter step   
through 00h to 40h to give us the address range (remember we're only   
interested in one RAM location per key. All other 6116 control lines   
should be set at the correct level (chip selects, output enables   
etcetera).

4 - Data word generator: For all unused keys we need to write 00h into   
their memory location to indicate they're not down, their memory location   
will contain the note number representing that key if on. To achieve this   
we need 6 AND gates (4081's?), we'll call the 2 input's "A" and "B" to   
make the explanation easier. Each "A" input is wired to the address   
counter outputs -  A0 through A5 are wired to AND gate inputs A0 through   
A5 (1 per gate), all the "B" inputs are tied together and linked to the 8   
input nand gate trigger, so, if a valid "key-down" comes back from the   
matrix - it triggers the nand gate which then enables *all* the AND gates   
to pass data on their "A" input to their outputs. E.g. if not triggered   
the outputs will remain low. The AND gate outputs 0 through 5 are now   
tied to the data bus pins D0-D5 on the 6116.

4 - Writing Data to memory: The whole idea of this circuit is to write   
into memory the state of the keyboard giving 00h if no key is down or the   
note number of the key(s) being played. We start scanning the keyboard at   
position 00 on the matrix - make this C0 if your using a 5 octave 61 key   
keyboard.C0 in this position would return 01 if down, C#0 would return   
02, D0 would return 03 and so on it can be expressed as follows

address 00 on matrix returns "1" , key=C0, address of RAM (writing) =   
00h, therefore 0000h *reads* "1" when accessed by an external device (C0   
key active).

Remember - all these functions are syncronised with the 555 clock. It   
would be a good idea to hold the address counter in RESET during the   
blanking period to force it tri-state (use the flip-flop that disables   
the  matrix drivers ) for external access to the RAM by another device,   
in this case the same should apply to the data lines / AND gates (not   
used - should be tri-state). Use a power on reset timer linked to all the   
reset lines. Some ancillary gates will be required to "share" some lines   
with another device.

I've just done this out of my head, like *now*. If there are any obvious   
mistakes in it please except my most humble appologies and I'll resign   
myself to telling jokes on the list <sniff> Shove this one in your pipe   
DIGISOUND!!!

Copyright 1996 the OB8 " Voltage Controlled Spiders".

Clive

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/<c.jones at sni.co.uk> / ...and on the 8th day
/01344 850213 Work   / God made Synthesizers
/01344 850209/291 Fax/ ...and God was called
/01628 602106 Home   /   ' Tom Oberheim '
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